An inter-integrated circuit (I2C) bus is a two-wire bidirectional serial bus and has a simple structure with two signal lines of a serial clock and serial data. Such a simple structure allows the I2C bus to be readily introduced.
When a plurality of I2C units are connected to the same I2C bus, a hang-up of any of the I2C units, for example, due to low stack which decreases a voltage level inside a signal line causes communications of the other I2C units to fail. In such a situation, a bus master unit connected to the I2C bus specifies and resets a hung-up bus slave unit based on the voltage of the serial data line of the I2C bus. Such a technique is disclosed in Japanese Laid-open Patent Publication No. 2010-055472, Japanese Laid-open Patent Publication No. 2005-004745, and Japanese Laid-open Patent Publication No. 2010-211810.
However, when an access abnormality occurs due to low stack in a bus master unit, for example, the conventional technique cannot determine whether the abnormality has occurred in a bus master unit side or an access destination of a bus slave unit side.